SIHG73N60E www.vishay.com vishay siliconix s12-0651-rev. b, 26-mar-12 1 document number: 91482 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 e series power mosfet features ? low figure-of-merit (fom) r on x q g ? low input capacitance (c iss ) ? reduced switching and conduction losses ? ultra low gate charge (q g ) ? avalanche energy rated (uis) ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? switch mode power supplies (smps) ? power factor correction power supplies (pfc) ?lighting - high-intensity discharge (hid) - fluorescent ballast lighting ? industrial - welding - induction heating - motor drives - battery chargers - renewable energy - solar (pv inverters) notes a. repetitive rating; puls e width limited by maximum junction temperature. b. v dd = 50 v, starting t j = 25 c, l = 28.2 mh, r g = 25 ? , i as = 12 a. c. 1.6 mm from case. d. i sd ? i d , di/dt = 30 a/s, starting t j = 25 c. product summary v ds (v) at t j max. 650 r ds(on) max. at 25 c ( ? )v gs = 10 v 0.039 q g max. (nc) 362 q gs (nc) 48 q gd (nc) 98 configuration single n-channel mosfet g d s to-247ac g d s ordering information package to-247ac lead (pb)-free SIHG73N60E-e3 lead (pb)-free and halogen-free SIHG73N60E-ge3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 600 v gate-source voltage v gs 20 gate-source voltage ac (f > 1 hz) 30 continuous drain current (t j = 150 c) v gs at 10 v t c = 25 c i d 73 a t c = 100 c 46 pulsed drain current a i dm 236 linear dera ting factor 4.2 w/c single pulse avalanche energy b e as 2030 mj maximum power dissipation p d 520 w operating junction and storage temperature range t j , t stg - 55 to + 150 c drain-source voltage slope t j = 125 c dv/dt 37 v/ns reverse diode dv/dt d 8.4 soldering recommendations (peak temperature) for 10 s 300 c c
SIHG73N60E www.vishay.com vishay siliconix s12-0651-rev. b, 26-mar-12 2 document number: 91482 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. c oss(er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 % to 80 % v dss . b. c oss(tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 % to 80 % v dss . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -40 c/w maximum junction-to-case (drain) r thjc -0.24 specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 600 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 250 a -0.65- v/c gate-source threshold voltage (n) v gs(th) v ds = v gs , i d = 250 a 2 - 4 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = 600 v, v gs = 0 v - - 1 a v ds = 480 v, v gs = 0 v, t j = 125 c - - 10 drain-source on-state resistance r ds(on) v gs = 10 v i d = 36 a - 0.032 0.039 ? forward transconductance g fs v ds = 40 v, i d = 10 a - 12 - s dynamic input capacitance c iss v gs = 0 v, v ds = 100 v, f = 1 mhz - 7700 - pf output capacitance c oss - 320 - reverse transfer capacitance c rss -5- effective output capacitance, energy related a c o(er) v ds = 0 v to 480 v, v gs = 0 v - 259 - effective output capacitance, time related b c o(tr) - 907 - total gate charge q g v gs = 10 v i d = 24 a, v ds = 480 v - 241 362 nc gate-source charge q gs -48- gate-drain charge q gd -98- turn-on delay time t d(on) v dd = 480 v, i d = 24 a, v gs = 10 v, r g = 10 ? -6395 ns rise time t r - 105 158 turn-off delay time t d(off) - 290 435 fall time t f - 120 180 gate input resistance r g f = 1 mhz, open drain - 1.52 - ? drain-source body diode characteristics continuous source-dra in diode current i s mosfet symbol showing the integral reverse p - n junction diode --73 a pulsed diode forward current i sm - - 200 diode forward voltage v sd t j = 25 c, i s = 36 a, v gs = 0 v - - 1.2 v reverse recovery time t rr t j = 25 c, i f = i s = 10 a, di/dt = 30 a/s, v r = 50 v - 688 - ns reverse recovery charge q rr -6.7-c reverse recovery current i rrm -19-a s d g
SIHG73N60E www.vishay.com vishay siliconix s12-0651-rev. b, 26-mar-12 3 document number: 91482 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage v ds , drain-to-source voltage (v) i d , drain-to-source current (a) 0 5 10 15 20 25 30 0 50 100 150 200 250 t j = 25 c top 15 v 14 v 13 v 12 v 11 v 10 v 5 v 6 v 7 v 8 v 9 v v ds , drain-to-source voltage (v) i d , drain-to-source current (a) 01020 5152530 0 30 60 90 120 150 5 v 6 v 7 v top 15 v 14 v 13 v 12 v 11 v 10 v 9 v 8 v t j = 150 c v gs , gate-to-source voltage (v) i d , drain-to-source current (a) 010 25 51520 0 50 100 150 200 250 t j = 25 c t j = 150 c t j , junction temperature (c) r d s (on) , drain-to- s ource 2.5 0.5 - 60 3 2 1.5 1 0 - 40 - 20 0 20 40 60 80 100 120 140 160 v gs = 10 v i d = 36 a on re s i s tance (normalized) v d s , drain-to- s ource voltage (v) capacitance (pf) 100 10 0 200 400 10 000 1 1000 100 300 500 600 c i ss c o ss c r ss v gs = 0 v, f = 1 mhz c i ss = c g s + c gd , c d s s horted c r ss = c gd c o ss = c d s + c gd 100 000 q g , total g ate charge (nc) v gs , g ate-to- s ource voltage (v) 16 4 0 24 20 12 8 0 60 120 180 240 300 360 420 480 v d s = 480 v v d s = 300 v v d s = 120 v
SIHG73N60E www.vishay.com vishay siliconix s12-0651-rev. b, 26-mar-12 4 document number: 91482 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 7 - typical source-dra in diode forward voltage fig. 8 - maximum safe operating area fig. 9 - maximum drain curre nt vs. case temperature fig. 10 - temperature vs. drain-to-source voltage fig. 11 - normalized thermal transient impedance, junction-to-case v s d , s ource-drain voltage (v) i s d , rever s e drain current (a) 0.1 1 10 100 1000 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 t j = 150 c t j = 25 c v gs = 0 v v d s , drain-to- s ource voltage (v) i d , drain current (a) * v gs > minimum v gs at which r d s (on) i s s pecified 0.01 0.1 1 10 100 1000 1 10 100 1000 1 m s i dm limited bvd ss limited 10 m s 100 s limited by r d s (on) * operation in thi s area limited by r d s (on) t c = 25 c t j = 150 c s ingle pul s e t j , case temperature (c) i d , drain current (a) 25 50 75 100 125 150 10 20 30 40 50 60 70 80 90 0 t j , junction temperature (c) v ds , drain-to-source 675 600 - 60 0 160 725 brakdown voltage (v) 700 650 625 575 - 40 - 20 20 40 60 80 100 120 140 550 750 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 normalized effective tran s ient thermal impedance pul s e time ( s ) duty cycle = 0.5 0.2 0.1 s ingle pul s e 0.05 0.02
SIHG73N60E www.vishay.com vishay siliconix s12-0651-rev. b, 26-mar-12 5 document number: 91482 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 12 - switching time test circuit fig. 13 - switching time waveforms fig. 14 - unclamped inductive test circuit fig. 15 - unclamped inductive waveforms fig. 16 - basic gate charge waveform fig. 17 - gate charge test circuit pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f r g i as 0.01 t p d.u.t l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
SIHG73N60E www.vishay.com vishay siliconix s12-0651-rev. b, 26-mar-12 6 document number: 91482 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 18 - for n-channel vishay siliconix maintains worldwide manufactu ring capability. products may be manufact ured at one of seve ral qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91482 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd
package information www.vishay.com vishay siliconix revision: 18-mar-13 1 document number: 91360 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to-247ac (high voltage) notes 1. dimensioning and tolera ncing per asme y14.5m-1994. 2. contour of slot optional. 3. dimension d and e do not include mold fl ash. mold flash shal l not exceed 0.127 mm (0.005") per side. these dimensions are mea sured at the outermost extremes of the plastic body. 4. thermal pad contour optional with dimensions d1 and e1. 5. lead finish uncontrolled in l1. 6. ? p to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154"). 7. outline conforms to je dec outline to-247 with exception of dimension c. 8. xian and mingxin actually photo. millimeters inches millimeters inches dim. min. max. min. max. dim. min. max. min. max. a 4.58 5.31 0.180 0.209 d2 0.51 1.30 0.020 0.051 a1 2.21 2.59 0.087 0.102 e 15.29 15.87 0.602 0.625 a2 1.17 2.49 0.046 0.098 e1 13.72 - 0.540 - b 0.99 1.40 0.039 0.055 e 5.46 bsc 0.215 bsc b1 0.99 1.35 0.039 0.053 ? k 0.254 0.010 b2 1.53 2.39 0.060 0.094 l 14.20 16.25 0.559 0.640 b3 1.65 2.37 0.065 0.093 l1 3.71 4.29 0.146 0.169 b4 2.42 3.43 0.095 0.135 n 7.62 bsc 0.300 bsc b5 2.59 3.38 0.102 0.133 ? p 3.51 3.66 0.138 0.144 c 0.38 0.86 0.015 0.034 ? p1 - 7.39 - 0.291 c1 0.38 0.76 0.015 0.030 q 5.31 5.69 0.209 0.224 d 19.71 20.82 0.776 0.820 r 4.52 5.49 0.178 0.216 d1 13.08 - 0.515 - s 5.51 bsc 0.217 bsc ecn: x13-0045-rev. c, 18-mar-13 dwg: 5971 0.10 a c m m e e/2 (2) (4) r/2 b 2 x r s d see view b 2 x e b4 3 x b 2 x b2 l c l1 1 2 3 q d a a2 a a a1 c ? k b d m m a ?p (datum b) ?p1 d1 4 e1 0.01 b d m m view a - a thermal pad d2 dde e c c view b (b1, b3, b5) base metal c1 (b, b2, b4) section c - c, d - d, e - e (c) planting 4 3 5 7 5 5
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